1. Field of the Invention
The present invention relates to a trim fuse circuit, and more particularly, to a trim fuse circuit capable of disposing trim conducting pads on scribe lines of a wafer.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a voltage reference circuit 100. The voltage reference circuit 100 is utilized to generate a reference voltage VREF with a magnitude decided by the reference circuit 100. As shown in FIG. 1, the voltage reference circuit 100 comprises a constant current source IREF, five resistors R1, R2, R3, R4, and R5, and four switches SW1, SW2, SW3 and SW4. The current generated by the constant current source IREF is set as 1 micro-Amp and the five resistors R1˜R5 are all set as 1 mega-ohm. The switches SW1˜SW4 respectively short out the corresponding resistors according to the switch control signals S1˜S4. If the switch control signal is logic “0” (low voltage level), the switch is turned off. On the contrary, if the switch control signal is logic “1” (high voltage level), the switch is turned on and the corresponding resistor is short-circuited. For example, when switch control signal S1 is logic “0”, the switch SW1 is turned off so that the current from the constant current source IREF passes through the resistor R1 and a voltage drop over the resistor R1 is generated. When switch control signal S1 is logic “1”, the switch SW1 is turned on so that the current from the constant current source IREF passes through the switch SW1 and no voltage drop is generated. As shown in FIG. 1, when the switch control signals S1˜S4 are set as [1111], the switches SW1˜SW4 are turned on so that the generated reference voltage VREF is 1 volt (VREF=IREF×R5=1×1=1). When the switch control signals S1˜S4 are set as [1110], the switches SW1˜SW3 are turned on and the switch SW4 is turned off. Consequently, the generated reference voltage VREF is 2 volts (VREF=IREF×(R4+R5)=1×2=2) and so on. Therefore, the reference voltage VREF can be adjusted as required according to the switch control signals S1˜S4.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating a conventional trim fuse circuit 200. The trim fuse circuit 200 is utilized for generating the switch control signals S1˜S4. The user can set the status of the trim circuit 200 in order to set the logic (voltage level) of the switch control signals S1˜S4. The trim fuse circuit 200 comprises four fuse sets 211, 212, 213 and 214, a trim control module 220 and a current control module 230.
The current control module 230 comprises a transistor Q1 and a constant current source IREF. The current control module 230 is utilized to form current mirrors with the transistors Q11, Q21, Q31 and Q41 in the fuse sets 211, 212, 213 and 214 for duplicating currents with the same magnitude as the current from the constant current source IREF. A first end (source) of the transistor Q1 is electrically connected to a voltage source VDD (for example, 5 volt). A second end (drain) of the transistor Q1 is electrically connected to the constant current source IREF. A control end (gate) of the transistor Q1 is electrically connected to the second end of the transistor Q1 and the control ends of the transistors Q11, Q21, Q31, and Q41. The constant current source IREF is electrically connected between the second end of the transistor Q1 and a voltage source VSS (for example, a ground end, 0 volt). The transistor Q1 can be a P channel Metal Oxide Semiconductor (PMOS) transistor.
The fuse sets 211˜214 are respectively utilized to provide the logic (voltage level) of the switch control signals S1˜S4. That is, after the trim control module 220 trims, the fuse sets 211˜214 generate the switch control signals S1˜S4 with the fixed logic. The fuse sets 211˜214 have the same structure, so only the fuse set 211 is illustrated and the description of the rest fuse sets is similar and will not be repeated again. The fuse set 211 comprises two transistors Q11 and Q12, a fuse PF1 and an inverter INV1. A first end (source) of the transistor Q11 is electrically connected to the voltage source VDD. A second end (drain) of the transistor Q11 is electrically connected to a second end (drain) of the transistor Q12. A control end (gate) of the transistor Q11 is electrically connected to the control end of the transistor Q1. In this way, the transistor Q11 can form a current mirror with the transistor Q1 for duplicating the current from the constant current source IREF. A first end (source) (the node N1) of the transistor Q12 is electrically connected to the resistor RCOM and the common trim conducting pad of the trim control module 220 through the fuse PF1. A second end (drain) of the transistor Q12 is electrically connected to a second end of the transistor Q11. A control end (gate) of the transistor Q12 is electrically connected to the second end of the transistor Q12. Thus, the transistor Q12 is utilized as a diode. The input end of the inverter INV1 is electrically connected to the node N1. The output end of the inverter INV1 outputs the switch control signal S1 according to the voltage level on the input end of the invert INV1 (the voltage level on the node N1). The inverter INV1 can be designed that when the voltage level on the input end of the inverter INV1 is higher than 2 volts (the voltage level on the node N1 higher than 2 volts), the output (switch control signal S1) of the inverter INV1 is logic “0”, and when the voltage level on the input end of the inverter INV1 is lower than 0.5 volt (the voltage level on the node N1 lower than 0.5 volt), the output (switch control signal S1) of the inverter INV1 is logic “1”.
In addition, the transistor Q11 can be a PMOS transistor and the transistor Q12 can be an N channel Metal Oxide Semiconductor (NMOS) transistor. The fuse PF1 can be a poly-silicon fuse with an impedance about 99 ohms.
The trim control module 220 comprises four trim conducting pads PT1, PT2, PT3 and PT4, a common trim conducting pad PCOM and a resistor RCOM. The trim conducting pads PT1, PT2, PT3 and PT4 are respectively electrically connected to the nodes N1, N2, N3 and N4. The common trim conducting pad PCOM is electrically connected to all the fuses PF1˜PF4. The resistor RCOM is electrically connected between all the fuses PF1˜PF4 and the voltage source VSS and is utilized as a pull-low resistor. The impedances of the fuses PF1˜PF4 limit the currents passing through the fuses PF1˜PF4 during the prediction phase to prevent the fuses PF1˜PF4 from being burned out.
During the prediction phase, the trim conducting pads PT1˜PT4 are utilized to receive the trim prediction voltages (for example, 2 volts or 0 volt) and transmit the received trim prediction voltages to the corresponding inverters for predicting if the generated logic of the switch control signals are as required. During the trim phase, the trim conducting pads PT1˜PT4 are utilized to receive the trim set voltage (for example, 5 volt) and the common trim conducting pad Pow is utilized to receive the trim common voltage (for example, 0 volt) for trimming the fuses as desired.
For example, during the prediction phase, the trim conducting pad PT1 receives a voltage with 2 volts and transmits to the node N1 (the input end of the inverter INV1). As a result, the switch control signal S1 outputted from the inverter INV1 during the prediction phase is logic “0”. On the contrary, during the prediction phase, the trim conducting pad PT1 receives a voltage with 0 volt and transmits to the node N1 (the input end of the inverter INV1). As a result, the switch control signal S1 outputted from the inverter INV1 during the prediction phase is logic “1”.
After the prediction phase, if the switch control signal is determined to be logic “0”, during the trim phase, the trim conducting pad PT1 receives a trim set voltage with 5 volts and the common trim conducting pad PCOM receives a trim common voltage with 0 volt. Consequently, the voltage drop across the fuse PF1 is 5 volts so that a large current passes through and burns out the fuse PF1 and the connection established by the fuse PF1 is broken (open-circuited). In such condition, the node N1 is not electrically connected to the voltage source VSS through the fuse PF1 and the resistor RCOM and does not keep at a low level. Instead, the node N1 is electrically connected to the voltage source VDD through the transistors Q11 and Q12 so as to keep at a high voltage level (higher than 2 volts). Thus, the inverter INV1 outputs the switch control signal S1 with the logic “0”.
On the contrary, after the prediction phase, if the switch control signal is determined to be logic “1”, during the trim phase, the trim conducting pad PT1 does not receive the trim set voltage with 5 volts. That is, the voltage on the trim conducting pad PF1 is floating. The common trim conducting pad PCOM still receives the trim common voltage with 0 volt. Consequently, there is no voltage drop across the fuse PF1 so that no large current passes through the fuse PF1 and the fuse PF1 is not burned out. In such condition, the node N1 is electrically connected to the voltage source VSS through the fuse PF1 and the resistor RCOM so as to keep at a low voltage level (lower than 0.5 volt). Thus, the inverter INV1 outputs the switch control signal S1 with the logic “1”.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating the conventional trim fuse circuit 200 during the prediction phase. During the prediction phase, different trim prediction voltages (for example, 0 volt or 2 volt) can be set on the trim conducting pads PT1˜PT4 so that the inverters INV1˜INV4 generate the corresponding switch control signals S1-S4 accordingly. In such condition, the reference voltage VREF is obtained from the reference voltage circuit 100 controlled by the switch control signals S1˜S4 which are determined in the prediction phase. If the obtained reference voltage VREF is as desired, then the trim fuse circuit 200 enters the trim phase to trim the fuses to be trimmed; if not, different trim prediction voltages are set on the trim conducting pads PT1˜PT4 over and over again so that the inverters INV1˜INV4 generate the corresponding switch control signals S1˜S4 accordingly until the obtained reference voltage VREF is as desired. As shown in FIG. 3, the trim conducting pads PT1, PT2, PT3 and PT4 respectively receive the trim prediction voltages with 2, 0, 2, and 0 volts. As a result, the switch control signals S1˜S4 generated from INV1, INV2, INV3, and INV4 are [0101]. According to the logic of the switch control signals S1˜S4 ([0101]), the voltage reference circuit 100 generates the reference voltage VREF with 3 volts (VREF=1×(R1+R3+R5)=1×(1+1+1)=3). If the required voltage level of the reference voltage is 3 volts, then the trim fuse circuit 200 enters the trim phase for trimming the fuses required to be burned out.
Please refer to FIG. 4. FIG. 4 is a diagram illustrating the conventional trim fuse circuit 200 during the trim phase. According to the FIG. 3, it is known that the switch control signals S1˜S4 are [0101] eventually. That is, the fuses PF1 and PF3 are required to be trimmed (burned out) so that the connections established by the fuses PF1 and PF3 are broken (open-circuited). In this way, the nodes N1 and N3 keep at the high voltage level respectively by being electrically connected to the voltage source VDD through the transistors Q12 and Q32. Therefore, the inverters INV1 and INV3 output the switch control signals S1 and S3 with logic “0”. The fuses PF2 and PF4 are not required to be trimmed (burned out). Thus, the nodes N2 and N4 still keep at the low voltage respectively by being electrically connected to the voltage source VSS through the fuses PF2, PF4 and the resistor RCOM so that the inverters INV2 and INV4 output the switch control signals S2 and S4 with logic “1”. Consequently, during the trim phase, for burning out the fuses PF1 and PF3, the received voltages on trim conducting pads PT1 and PT3 are required to be 5 volts and the received voltage on the common conducting pad PCOM are required to be 0 volt so that the large currents pass through and burn out the fuses PF1 and PF3.
However, the trim conducting pads PT1˜PT4 are required to use probe-contacting for receiving the trim prediction voltages or the trim set voltages. As a result, the areas of the trim conducting pads PT1˜PT4 must be large enough. In such condition, if the trim conducting pads PT1˜PT4 are disposed in the chips on the wafer, the available area in the chips decreases extremely. Consequently, by means of the conventional technology, the trim conducting pads PT1˜PT4 are disposed on the scribe lines of the wafer for increasing the available area in the chips.
Please refer to FIG. 5. FIG. 5 is a diagram illustrating the trim conducting pads being disposed on the scribe line when a wafer is being scribed. As shown in FIG. 5, because the trim conducting pads PT1˜PT4 are disposed on the scribe line of the wafer, when the wafer is scribed to generate chips, the trim conducting pads PT1˜PT4 are scribed as well. In general, all of the trim conducting pads are made in metal. Since the metal has good malleability, the trim conducting pads PT1˜PT4 may be stretched because of being scribed, and therefore contact the substrate of the wafer. Generally speaking, the substrate of the P-type substrate wafer is utilized to be the common voltage source VSS (ground end, 0 volt) and the substrate of the N-type substrate wafer is utilized to be the common voltage source VDD (for example, 5 volts). Thus, after being scribed, the trim conducting pads PT1˜PT4 are possible to receive the voltage provided by the voltage sources VDD or VSS and the switch control signals are affected so that the actual reference voltage is different from expected.
Please refer to FIG. 6. FIG. 6 is a diagram illustrating that the trim conducting pad contacts the substrate of the wafer, causing the incorrect switch control signals. The fuse set 212 is illustrated in FIG. 6. The rest fuse sets can be derived and not to be repeated again. Suppose that the substrate of the wafer shown in FIG. 6 is the N-type substrate. After the prediction phase shown in FIG. 3 and the trim phase shown in FIG. 4, the fuse PF2 of the fuse set 212 is determined not to be trimmed (burned out) so that the voltage on the node N2 is pulled to be at the low voltage level by being electrically connected to the voltage source VSS through the resistor RCOM. Hence, the switch control signal S2 outputted from the inverter INV2 is logic “1”. However, after being scribed, the trim conducting pad PT2 is stretched to be electrically connected to the N-type substrate. Therefore, the trim conducting pad PT2 receives the voltage provided by the voltage source VDD (for example, 5 volts) and transmits the received voltage to the node N2. In this way, the voltage on the node N2 is raised up to the high voltage level due to the voltage source VDD. It means that the switch control signal S2 outputted from the inverter INV2 becomes logic “0” and not to be the required logic “1”. In such condition, the obtained reference voltage is not as the same as expected, which causes inconvenience.